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1/23 AN1299 application note march 2001 devices family the st l638x family includes four control ics: l6384, l6385, l6386 and l6387. they are realized in bcd off line technology: they are able to operate at voltage up to 600v. the logic inputs are cmos logic compatible and the driving stages can source up to 400ma and sink 600ma. the bootstrap diode is integrated inside the ics helping to reduce the pcb parts number and to increase the layout flexibility. internal diode structure figure 1. integrated bootstrap diode (principle schematic) to load d00in1163 h.v. hvg ab lvg hvg lvg c boot to load h.v. c boot d boot v boot v cc v cc v out v boot v out external bootstrap diode lin internal bootstrap diode structure by gian paolo meloncelli l638x tricks and tips topics covered: ? devices family ? internal diode structure ? how to select cboot ? parasitic elements in the half bridge topology ? how to manage below ground voltage on out pin: ? out pin voltage that persists below the signal ground ? undershoot spike on the out pin ? tricks and layout suggestions ? l6386: how to deal with signal ground and power ground
AN1299 application note 2/23 a floating supply is required to drive the high voltage section and the high side switch gate. for this reason we must use the bootstrap principle, normally accomplished by an high voltage fast recovery diode (fig.1a). the bootstrap capacitor is charged when the vout become below the ic supply voltage: in this situation the current flows from the ic supply (vcc pin) to the capacitor (fig.2). when the out pin is pulled up near to the high voltage rail (the low side switch is turned off and the high side switch on), the diode is reverse biased and the capacitor can ofly upo to the level of the high voltage bus plus vcc. the high voltage section is supplied only by the boot- strap capacitor. in the l638x family a patented integrated structure replaces the external diode. it is realized by an high voltage dmos (typical rdson 125 w ) driven synchronously with the low side driver (lvg), with a diode in series, as in- dicated in fig 1b. when the internal bootstrap structure is used we have to remember that: 1. the ointernal diodeo is a structure, and not an integrated discrete diode: this means that the diode structure is turned on (and it behaves like an external diode) only when the low side driver is on. 2. when the low side driver is turned on, out pin voltage must be below the ic supply: otherwise the current can not flow from the supply to the bootstrap capacitor (fig 2). figure 2. bootstrap capacitor charging path the following picture (figure 3a) shows an example in which the internal bootstrap diode can not be used: when the low side driver is on (fig.3b) the voltage at the out pin is held to the high voltage bus and the current can not charge the bootstrap capacitor. the out pin voltage goes below the ic supply voltage 0v only when vinput is low (vout=-vf-rsense*iload): but in this situation the internal diode is off, and the charging current can not flow in the capacitor. for more detailed information on the internal diode behavior see an1263 ousing the internal bootstrap charge capability of the l6384, 85, 86 and 87 in driving a six transistor inverter bridgeo. d00in1164 hvg lvg to load h.v. c boot v cc v boot v out lin bootstrap current path
3/23 AN1299 application note figure 3. in this example the external diode is mandatory. (b) vinput high - current path - (c) vinput low - current path - (a) h.v. a rg1 q2 l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rsense q1 d1 boot diode d2 vinput vcc cboot h.v. vout=h.v.(>vcc) a rg1 q2 l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rsense q1 d1 boot diode d2 vinput vcc cboot h.v. vout=vf-rsense*iload a rg1 q2 l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rsense q1 d1 boot diode d2 vinput vcc cboot d00in1165
AN1299 application note 4/23 how to select c boot as already said, when the internal bootstrap diode is used, the bootstrap capacitor is charged every time the low side driver is on and the out pin is below the ic power supply. the capacitor is discharged only when the high side switch is turned on: this capacitor is the supply for the high voltage section. let us discuss how to select the right capacitor value. the dimensioning procedure that we are going to describe is valid for both cases: with or without the external diode. the first parameter to take into account is the maximum voltage drop that we have to guarantee when the high side switch is in on state. the maximum allowable voltage drop ( d v boot ), depends on the minimum gate drive voltage (for the high side switch) that we want to maintain. if v gs-min is the minimum gate source voltage, the capacitor drop must be : v cc : ic voltage supply v f : bootstrap diode forward voltage the capacitor size is calculated by the formula : q tot : total amount of the charge supplied by the capacitor. this is evaluated taking into account the following factors: i. q gate : high side switch total gate charge ii. i lk_gs : high side switch gate-source leakage current iii. i lk_cap : bootstrap capacitor leakage current iv. i qbs : bootstrapped section quiescent current v. i lk : bootstrapped section leakage current vi. q ls : charge required by the internal level shifter (3nc for all l638x drivers) vii. t on : high side switch on time viii. i lk_diode : external diode leakage current (if it is used). the total charge supplied by the bootstrap capacitor will be: q tot =q gate +(i lk_cap +i lk_gs +i qbs +i lk +i lk_diode )t on +q ls the capacitor leakage current is important only if an electrolytic capacitor is used, otherwise this term can be neglected (e.g. with ceramic capacitor). when the internal diode is used, the dmos rdson introduces an additional voltage drop that can be low at low switching frequency. increasing the frequency this drop can be evaluated as follow: i charge : capacitor charging current. r dson : dmos drain-source typical on resistance. t charge : capacitor charging time (it is the low side turn on time). v boot d v cc v f v gs_min = c boot q tot v boot d ------------------ = v drop i ch e arg r dson ? q tot t ch e arg -------------------- r dson ? ==
5/23 AN1299 application note this drop must be taken into account when the maximum d v boot is calculated. if this drop is too high or the circuit topology does not allow a sufficient charging time, an external fast recovery diode can be used. example: let's evaluate the bootstrap capacitor size when (the internal diode is used) . data: oq gate = 70nc (stgw12nb60h) oi lk_gs = 100na oi qbs =200 m a (datasheet l6386) oi lk =10 m a (datasheet l6386) oq ls =3nc ot on =100 m s capacitor leakage current is not considered because we assume we use a ceramic capacitor and not an elec- trolytic one. if the maximum allowable voltage drop on the bootstrap capacitor is 1 v during the high side switch on state, the minimum capacitor size is: the voltage drop due to the internal dmos rdson is nearly: and can be neglected. we have assumed the capacitor charging time equal to the high side on time (duty cycle 50%). according to different bootstrap capacitor sizes we may have the following drops: o 100nf --> , o 150nf --> , o 220nf --> suggested values are within the range of 100nf-570nf but the right value must be selected according to the application in which the device is used, when the capacitor size is too big, the bootstrap charging time is slowed and the low side on time (i.e. the ointernal diodeo on time) might be not long enough to reach the right bootstrap voltage. c boot q tot v boot d ------------------- 94nc 1v --------------- 94nf === v drop q tot t ch e arg -------------------- r dson ? 94nc 100 m s ----------------- 125 w ? 117mv === v boot d q tot c boot --------------- 0.93v == v boot d q tot c boot --------------- 0.62v == v boot d q tot c boot --------------- 0.42v ==
AN1299 application note 6/23 parasitic elements in the half bridge topology parasitic elements exist inside a half bridge driver circuit and they have to be considered because switching currents rapid changes induce voltage transients across all the parasitic components. in the following paragraphs we are going to describe the use of l6386 in a typical half bridge application and the layout parasitic elements to minimize in order to improve the application behavior (see fig.4). we take the l6386 device as example, but the considerations that we do can be used also for all l638x drivers. figure 4. main parasitic elements that must be taken into account inside the half bridge topology. pard2 pard1 pars2 par loop pars1 (out) rg1 rg1_off rg2_off l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rsense q1 cboot q2 bulk capacitor d01in1173 h.v. ba
7/23 AN1299 application note 1 how to manage below ground voltage on the out pin we have to take care of the below ground voltage on the out pin because they are really pernicious. there are two main issues: 1) out pin voltage persists below the signal ground reference during all the time in which the low side freewheeling diode is in conduction state. (static condition) 2) undershoot spike on the out pin that appears during the commutation pattern. (dynamic condition) in the following sections let's analyze both the issues and what could happen to the ic. 1.1 out pin voltage that persists below the signal ground figure 5. voltage across the bootstrap capacitor. in static mode the out pin can sustain below ground voltages down to -3v (absolute maximum rating). within this limit, a negative voltage on the out pin can cause the bootstrap capacitor overcharge. this condition hap- pens when the load current flows in the direction shown in fig.5a: the high side is off and the low side freewheel- ing diode is on. in this condition the voltage between the out pin and the ground is: v out =-(r sense +r trace )i load -v f where v f is the freewheeling diode forward voltage, rtrace is the parasitic trace resistance, rsense the sense resistor and iload is the load current. we have not mentioned the parasitic trace inductance because we are not dealing with dynamic undershoot voltage. the voltage across the cboot is: v boot =v cc -v out =v cc +(r sense +r trace )i load +v f it has to be: v boot < 17v (recommended operating condition for all the three l638x drivers). the bootstrap ca- pacitor is the supplier of the internal high voltage driver, and if this voltage goes above the recommended con- dition the device could fail. l1 hvg hvg v out v cc v cc lvg load iload h.v. c boot v f r sense *i load undershootspike bloelowground ocontinouso \voltage h.v. vout 0v (a) (b) t d01in1176
AN1299 application note 8/23 in order to avoid this undesired phenomena we suggest the following oruleso: maintain a osafety margino when the v cc is selected: for example, if we use v cc = 15v and we want to avoid that the bootstrap capacitor becomes overcharged (i.e. charged over 17v), the out pin must not go below ground more than -2v. the higher vcc, the lower below ground voltage on the out pin. select the rsense and minimize rtrace in order to satisfy the the following relation: vboot = vcc - vout = vcc + (r sense +r trace )i load +v f <17v 1.2 undershoot spike on the out pin: if the out pin undershoot spike has a time length that is in order of tenths of nanoseconds the bootstrap capac- itor can not become overcharge. figure 6. equivalent internal bootstrap charging circuit. we can evaluate the maximum below ground duration that can lead to capacitor overcharge. let us assume that the below ground spike has not a triangular shape but a square shape, like the dotted line in the fig. 6a (worst case). if we have: ov cc =15 oc boot = 100nf ov f = 0.7v ov out = 18v (below ground spike on the out pin) o d v boot =17v-15v=2v (maximum allowable capacitor overcharge voltage ) the max below ground spike duration is : dmos rdson 125 w v cc v cc c boot v out v boot v f below ground spike h.v. vout 0v (a) (b) d t d01in1177 t d r dson c boot ln v out v f v out v f v boot d ----------------------------------------------- ?? ?? ?? 1.5 m s @ ?? =
9/23 AN1299 application note it is much more than some tenths of nanoseconds! note that in this example we use the internal bootstrap diode. if an external diode is adopted, the situation may become more dangerous: infact in this case the internal dmos rdson resistance does not limit the bootstrap capacitor overcharge. the example above demonstrates that short undershoot spikes on the out pin do not lead to bootstrap over- charge. they are dangerous for another reason: heavy below ground spikes can lead to a spurious logic com- mutation of the ic. it can happen that the high side or the low side buffer do not follow the input logic signals. a consequence of this situation is power switch cross-conduction and/or device damage. this situation is caused by the parasitic inductance in the tracks between the out node and ground, we have called them pard1 and pars1 in the fig. 4. now we will analyze the following points: 1. how to measure the below ground spike on the out pin? 2. what are the root causes? 3. dealing with the undershoot spikes - tricks and layout suggestions. 1.2.1 how to measure the below ground spike on the out pin? the voltage difference between the out pin and the signal ground is one of the first signals that has to be ana- lyzed with the oscilloscope when the driver outputs do not follow the logic inputs or when the device has a ogen- eralo failure. it is very important to put the ground probe as close as possible to the ic signal ground pin and not to a generic ground. if the ground probe is not well connected to a point that is close to the ic pin, a lot of noise and strange spurious spikes could be seen, due to the high current that can flows into the ground tracks of the application. figure 7. where to put the oscilloscope probe for the undershoot spike measurement. pard2 pard1 pars2 to load pars1 (out) rg1 rg1_off rg2_off l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rsense 0.1 w q1 cboot q2 bulk capacitor d01in1178 h.v. ba probe here undershoot spike vout-sground t
AN1299 application note 10/23 1.2.2 what are the root causes ? let's find the undershoot spike root causes. there are two main causes: i. tracks parasitic inductance ii. high di/dt values we can use the well known formula: where l = pard1 + pars1 (referring to fig. 4). note that the parasitic inductance pard2 and pars2 are not in- volved in the path that can lead to the undershoot voltage on the out pin. let's analyze the current path during the high and low side commutation when the direction of the load current is positive or negative. (see fig. 8) figure 8. pcb trace parasitic inductance that must be minimized. i load >0: in this condition the undershoot spike at the out pin appears when the high side is switched off and the load current must flow through the low side freewheeling diode. the below ground spike in this condition is: the peak voltage is mainly composed by the l*di/dt and vfpk contribute, all other terms are negligible. vfpk: the diode usually has a forward voltage around 1v but shows a forward peak voltage that depends on the di/dt current and on the diode technology. the higher di/dt, the higher peak forward voltage across the di- ode(fig.9 ). v d l dl dt ---- - ? = pard2 pard1 pars2 iload load parasitic inductance that lead to undershoot spike on the out pin pars1 (out) rg1 rg1_off rg2_off l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rsense 0.1 w q1 cboot q2 bulk capacitor d01in1179 h.v. bus b iload<0 iload>0 t a v peak v fpk l di dt ---- - r sense r trace + () i load ? + ? + =
11/23 AN1299 application note figure 9. diode transient forward peak voltage versus di/dt (stta806). high side on-low side off figure 10. the low side device is off and the load current flows in the high side power switch (on) pard2 high side on pard1 pars2 load pars1 (out) rg1 rg1_off rg2_off l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rsense 0.1 w q1 cboot q2 bulk capacitor d01in1180 h.v. bus ba
AN1299 application note 12/23 high side off -low side off figure 11. the high side is turned off and the load current flows trough the low side freewheeling diode that is injected figure 12. the oscilloscope image shows how the undershoot spike on the out pin is handled with the high side turn off resistor (rg2_off).note that all the measurements shown are done with the low side always off. pard2 high side off recirculation path pard1 pars2 load pars1 (out) rg1 rg1_off rg2_off l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rsense 0.1 w q1 cboot q2 bulk capacitor d01in1181 h.v. bus ba isource vout vgate isource vout vgate di/dt=130 a/us vgate vout isource di/dt=110 a/us di/dt=100 a/us vgate vout isource zoomed images r g2-off =0 w r g2-off =22 w r g2-off =56 w
13/23 AN1299 application note in order to reduce this undershoot voltage we can act on: reducing the parasitic l between the out and the ground connection. reducing the di/dt: this is accomplished by increasing the high side turn off resistor. this has the double effect to reduce the low side diode forward peak voltage and the parasitic inductance contribution .disadvantage: the switching power losses increase. during the high side turn-on, on the out pin we can see only an overshoot spike but in most of cases this is not dangerous for the ic due to the high voltage capability of these l638x drivers (600v is the absolute maximum on the out pin). n i load <0: in this load condition the bigger undershoot spike on the out pin occurs when the low side switch is turned on during the high side freewheeling diode conduction state. the spike is mainly related to the freewheeling diode behavior. high side off - low side off figure 13. the low side mos is off and the load current flows inside the high side freewheeling diode pard2 low side off pard1 pars2 load pars1 (out) rg1 rg1_off rg2_off l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rsense 0.1 w q1 cboot q2 bulk capacitor d01in1182 h.v. bus ba
AN1299 application note 14/23 high side off-low side turned on figure 14. the low side is turned on, the current that flows through the low side switch is the sum of the charge recovered by the diode (qrr) and the load current high side off - low side on figure 15. now the high side freewheeling diode is reverse biased and the current that flows through the low side switch is only the load current pard2 low side on freewheeling current pard1 pars2 load pars1 (out) rg1 rg1_off rg2_off l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rsense 0.1 w q1 cboot q2 bulk capacitor d01in1183 h.v. bus ba pard2 low side on pard1 pars2 load pars1 (out) rg1 rg1_off rg2_off l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rsense 0.1 w q1 cboot q2 bulk capacitor d01in1184 h.v. bus ba
15/23 AN1299 application note figure 16. undershoot caused by the freewheeling diode. the high side freewheeling diode is for- ward biased by the load current and the low side switch is turned on, so the current shown in the picture is the sum of the load current and the diode recovered charge. the picture above(fig.16) shows how the high di/dt diode recovery current leads to a heavy spike below ground on the out pin. all the charge recovered by the high side diode goes through the low side switch when it turns on .the current in the low side drain ramps up with a controlled slope (slope a) that is related only to the low side turn-on speed. on the other side the slope (slope b) is not well olimitedo: the high di/dt value (b) depends mainly on the diodes physical structure. in this case the peak voltage could be reduced by acting on the pcb traces, reducing the parasitic inductance, designing wider and shorter traces. but, attention must be paid also to the diode selection. a very high value of diode recovered current slope is very difficult to manage anyway and forces to use higher values of low side turn on resistance: this for sure helps to reduce the below ground spikes, but increases the turn on speed and the switching losses. the turn on resistor value should be as low as the layout allows. for example, referring to fig16c, if we want to limit the undershoot spike under 10v, with the same low side turn on resistance, and we have 700a/ m s of di/dt (we are talking about the second slope (b) of the current shown in the picture 16c) we need a maximum parasitic inductance of 15nh: difficult to reach. so in this case we must increase the low side turn on resistance increasing the switching losses. the message is to reduce as much as possible the trace parasitic inductance, but also to take into account the amount of the total freewheeling diode recovered charge and the diode softness factor. low side ron = 100 w low side ron = 220 w low side ron = 560 w (a) (b) undersho spike diode recovered current load current low di/dt (a) high di/dt (b) (p) vout [5 0v/div] idrain [ 5a/div] (c) vout [50v/div] idrain [5a/div] (d) vout [50v/div] idrain [5a/div] (e) a load q2 rg1 rg2 cboot bulk capacitor q1 l6386 lin 1 sd 2 hin 3 n.c. 11 n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rsense 0.1ohm idrain vout rg2_off rg1_off hv bus
AN1299 application note 16/23 tricks and layout suggestions layout suggestions: the driver can easily deal with an undershoot spike in order of -18v (measured between the ic out pin and his signal ground) for a time that must not be longer than 100ns. the guidelines to follow in order to avoid device failure related to heavy below ground spikes are: n remember that the total amount of inductance and resistance exhibited is directly propor- tional to the trace's length and inversely proportional to its width. n to put both power switches of each half bridge as close as possible in order to make shortest and widest trace possible between the low side drain and the high side source. (this solution is in order to minimize the stray inductance pard1 and pars2 shown in fig.17) n take care of the trace between the low side source, the sense resistor and the power ground reference, making it shorter and wider.(to reduce pars1, fig.17). remember: all the load current flows in this path! figure 17. path to be optimized n use oinductance freeo sense resistors. n shorten the power switch lead length. tricks: n if we are not able to reduce the below ground spikes acting only on the layout a resistor in series to the out pin as indicated in (fig. 18) is a good trick that improves the device immunity. the resistor is not ad- ditional, the part count does not change , but it is the high side turn-off resistor that is moved on the out pin. in this way we can deal with undershoot spike above -18v. pard2 trace to be optimized pard1 pars2 load pars1 (out) rg1 rg1_off rg2_off l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rsense 0.1 w q1 cboot q2 bulk capacitor d01in1185 ba
17/23 AN1299 application note figure 18. placing resistance on the out pin this resistor, with values between 10-220 ohms, is not mandatory for the application, but helps to manage heavy below ground spikes. this limits the current absorbed from the ic substrate when the out pin voltage goes below the ground reference and improves the spike device immunity. we strictly suggest avoiding high resistor values, because it is in series with the bootstrap capacitor charging path. n another way to reduce the below ground spike is slowing down the switching speed by means of the gate resistor. when increasing the high side turn off series resistor the negative spikes amplitude de- crease, like shown in fig. 12. n pay attention selecting the freewheeling diodes, high values in terms of recovered charge can lead to high value of di/dt and then to spikes below ground on the out pin (fig.16).the only way to control this di/dt is increasing the low side turn on time by means of the turn on resistor, but this leads also to in- creasing in terms of switching losses. further suggestion : n the layout must also optimize the gate drive loops in order to improve mainly the power switch turn on immunity. high dv/dt values between power switch drain-source, inject current inside the gate drive path via the drain-gate capacitance. this impulsive current must be absorbed by the driver. but if the gate drive loop is not well optimized and has long and thin trace, the parasitic inductance can lead to the power switch turn on. this is called oinduced turn on o. to here load (out) rg1 rg1_off from here high side turn off resistor moved l6386 lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 rout rsense 0.1 w q1 cboot q2 bulk capacitor d01in1186 h.v. bus a
AN1299 application note 18/23 figure 19. (a) gate drive loops to be optimize and (b) current injected inside the low side gate drive loop.(the same concept is also valid for the high side gate drive loop) gate drive loop path load rg1 rg1_off l6386 l638x driver lin 1 sd 2 hin 3 11 n.c. n.c. 10 lvg 9 pgnd 8 vcc 4 diag 5 cin 6 sgnd 7 out 12 hvg 13 vboot 14 rg2 off rg2 rsense 0.1 w q1 cboot q2 bulk capacitor gate drive loop path q1 vds -vf h.v. vds q2 d d q2 turned on q1 held off by the driver during this transition the cgd inject charge into the gate loop path and can lead to gate source voltage and consequent low side power switch turn on. cgd cgs d01in1193 h.v. bus h.v. a (a) (b)
19/23 AN1299 application note how to deal with signal ground and power ground inside the l638x family the l6386 has two ground connections: n power ground: reference for internal low side power driver. on this ground circulate the low side gate loops current. n signal ground: reference for all the internal logic. on this reference flows only the logic supply current . figure 20. internal signal ground and power ground: simplified schematic two different grounds avoid that gate drive current flows on signal ground, leading to internal ground noise. control ground is extremely sensitive and separated grounds help to avoid that noise generated from the low side turn-offgate drive current reaches the internal logic section: noise generated on this signal grounds will keep inside the device and affecting the ic functioning. we can suggest two different ways to connect this ground references: 1. signal and power ground connected together (suggested solution); 2. signal and power ground separated. let's analyze both solutions: signal and power ground connected together connection between the two grounds is done in a specific point: common end of the current sense resistor. this point must be filtered with an electrolytic capacitor connected between ground and the high voltage bus. an high voltage ceramic capacitor connected in parallel with the electrolytic one is also advisable: this help to reduce the equivalent esr, and to smooth the high frequency voltage transient. h.v. section logic vref driver 4 1 2 3 5 6 lvg out hvg vboot 9 12 13 14 8 cin diag lin sd hin v cc sgnd pgnd 7 d01in1204
AN1299 application note 20/23 figure 21. signal ground and power ground connected together advantages: o the solution proposed helps to limit the noise seen by the signal ground due the low side turn off gate current. this current flows on the path highlighted in fig. 21. voltage transient on power ground pin due to parasitic inductance is not seen on signal ground. remember that turn-off gate current can be up to 600ma and can lead to heavy spikes on the ic power ground. o differential voltage between signal and power ground is minimized and due only to the low side gate drive current. there is no dc voltage between the two grounds but only transient voltage during the low side switch turn off. it is important to limit the transient voltage below ground on the pgnd to avoid in- ternal power drive damages. disadvantage: o pcb layout of the low side gate drive loop could be to olongo. if it is not well realized, his parasitic in- ductance and resistance could be not negligible. this means that we need to realize shorter and wider traces in order to minimize all the parasitic elements and improve the power switch oinduced turn onoim- munity. figure 22 show a bad way to connect signal and power ground, because all the load current flows on the para- sitic inductance inside the trace a, and can lead to high differential voltage between the two grounds. high current path low current path parasitic inductance common point rg2_on rg2_off rg1_off rg1_on rsense q1 cboot q2 bulk capacitor ceramic capacitor bias capacitor gate drive current loop h.v. bus h.v. section logic vref driver 4 1 2 3 5 6 lvg out hvg vboot 9 12 13 14 8 cin diag lin sd hin v cc sgnd pgnd 7 d01in1205
21/23 AN1299 application note figure 22. bad way to connect power and signal ground in a three phase motor control, three half bridges must be used: the ground's common point for all the three sections is highlighted in the figure 21. signal and power grounds must be connected at this point with a low inductive path (especially for the power ground connection). signal and power ground separated in this solution (fig.23), power ground is connected to the low side source and the sense resistor is outside the gate drive loop. the turn off resistor is moved from the low side gate to the o power ground-source patho like shown in figure 23: the resistor limits the current absorbed from the power ground when the voltage goes below the signal one. values suggested are the same that are also used for the turn off resistor: in the range of 10-100 ohms, or any- way more then 10 ohms. advantages: o noise seen by signal ground due the low side turn off gate current is limited.(as already said for the first solution) o low side gate drive loop is shorter if compared to the first solution (because the sense resistor is out- side of this loop). disadvantages: o differential voltage between the two grounds is proportional to the load current(see fig. 24 a,b). tran- sient and dc voltage difference could be high and leads to device damaging. in order to avoid ic failure is mandatory put the low side turn off resistor on the path shown in fig.23: this limits the current ab- sorbed from the power ground when his voltage goes below the signal one. high current path a low current path parasitic inductance rg2_on rg2_off rg1_off rg1_on rsense q1 cboot q2 bulk capacitor ceramic capacitor bias capacitor h.v. bus h.v. section logic vref driver 4 1 2 3 5 6 lvg out hvg vboot 9 12 13 14 8 cin diag lin sd hin v cc sgnd pgnd 7 d01in1206
AN1299 application note 22/23 figure 23. power ground connected to the low side source figure 24. voltage between power and signal ground for opposite load current directions rg2_on rg2_off rg1_off rg1_on rsense q1 cboot q2 bulk capacitor ceramic capacitor to here bias capacitor h.v. bus moved from here h.v. section logic vref driver 4 1 2 3 5 6 lvg out hvg vboot 9 12 13 14 8 cin diag lin sd hin v cc sgnd pgnd 7 d01in1207 rg2_on rg2_off rg1_off rg1_on rsense rsense*iload q1 cboot q2 bulk capacitor load ceramic capacitor to here bias capacitor h.v. bus moved from here h.v. section logic vref driver 4 1 2 3 5 6 lvg out hvg vboot 9 12 13 14 8 cin diag lin sd hin v cc sgnd pgnd 7 d01in1208 (a) rg2_on rg2_off rg1_off rg1_on rsense rsense*iload q1 cboot q2 bulk capacitor load iload iload ceramic capacitor to here bias capacitor h.v. bus moved from here h.v. section logic vref driver 4 1 2 3 5 6 lvg out hvg vboot 9 12 13 14 8 cin diag lin sd hin v cc sgnd pgnd 7 (b)
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